MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 432

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Address Bus (A[22:0]/SDA[13:0])
19.3 Address Bus (A[22:0]/SDA[13:0])
The 23 dedicated address signals, A[22:0], define the address of external byte, word, and
longword accesses. These three-state outputs are the 23 lsbs of the internal 32-bit address
bus and are multiplexed with the SDRAM controller row and column addresses
(SDA[13:0]).
Fourteen address signals are used for connecting to SDRAM devices as large as 256 Mbits.
The MCF5272 supports SDRAM widths of 16 or 32 bits. For a 32-bit width, SDRAM
address signals are multiplexed starting with A2. For a 16-bit width, address signals are
multiplexed starting with A1.
19.4 Data Bus (D[31:0])
The 32-bit, three-state, bidirectional, non-multiplexed data bus transfers data to and from
the MCF5272. A read or write operation can transfer 8, 16, or 32 bits in one bus cycle.
When a 16-bit data bus is used, mode parallel port C pins can be multiplexed onto D[15:0].
Data read from or written to on-chip peripherals is visible on the external data bus when the
device’s external bus width is 32 bits. When the device is configured for external 16-bit
wide data bus and the data access is 32 bits wide, the lower 16 bits of on-chip data are not
visible externally. On-chip cache, ROM, and SRAM accesses are not visible externally.
19.4.1 Dynamic Data Bus Sizing
When the device is in normal mode, dynamic bus sizing lets the programmer change data
bus width between 8, 32, and 16 bits for each chip select. The initial width for the bootstrap
program chip select, CS0, is determined by the state of BUSW[1:0]. The program should
select bus widths for the other chip selects before accessing the associated memory space.
BGA
Map
19-18
P10
P11
P12
P13
P14
Pin
P9
Table 19-2. Signal Name and Description by Pin Number (Continued)
0 (Reset)
OE/RD
PB11
PB15
CS2
CS6
R/W
Pin Functions
E_RxD3
E_MDC
1
–
–
–
–
MCF5272 User’s Manual
2
–
–
–
–
–
–
3
–
–
–
–
–
–
PB11/E_RxD3
PB15/E_MDC
CS6/AEN
OE/RD
Name
CS2
R/W
Port B bit 11/Rx data bit
3 (100 Base-T Ethernet
only)
Port B bit 15/
Management Channel
Clock (100 Base-T only)
Chip select 2
Chip select 6
Output enable/Read
Read/Write
Description
MOTOROLA
I/O
I/O
I/O
O
O
O
O