MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 447

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Physical Layer Interface Controller TDM Ports and UART 1
GCI mode: The DOUT0 output is for clocking data out of GCI port 0. DCL0 is twice the
bit rate (two clocks per data bit).
UART1: URT1_TxD is the transmitter serial data output for the UART1 module. The
output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in
the local loop back mode. Data is shifted out, least significant bit first, on this pin at the
falling edge of the serial clock source.
19.16.1.8 D-Channel Request(DREQ0/PA10)
IDL mode: This pin can be independently configured as the DREQ0 output for signaling to
a layer-1 S/T transceiver that a frame of data is ready to be sent on the port 0 D channel.
Port A mode: In GCI or IDL modes this pin can be independently configured as PA10.
19.16.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11)
QSPI mode: QSPI_CS1 is a QSPI peripheral chip select.
Port A mode: In GCI or IDL modes this pin can be independently configured as PA11.
19.16.2 GCI/IDL TDM Port 1
Physical Layer Interface port 1 is an additional GCI/IDL port. Also internally connected to
these pins are GCI/IDL serial ports 2 and 3.
19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT)
IDL mode: DCL1 is the data clock used to clock data in and out of the DIN1 and DOUT1
pins for IDL port 1. Data is clocked in to DIN1 on the falling edge of DCL1. Data is clocked
out of DOUT1 on the rising edge of DCL1.
GCI mode: GDCL1_OUT is used to clock data in and out of DIN1 and DOUT1 for GCI
port 1. DCL1 is twice the bit rate; that is, two clocks per data bit.
When this pin is configured as an output, the GDCL1_OUT clock signal from the on-chip
synthesizer clock generator is output on this pin. Also GDCL1_OUT is used to internally
drive all ports and delayed sync generators associated with ports 1, 2, and 3.
19.16.2.2 GCI/IDL Data Out (DOUT1)
IDL mode: The DOUT1 output is for clocking data out of IDL port 1. Data is clocked out
of DOUT1 on the rising edge of DCL1. DOUT1 is also used for clocking data from ports
2 and 3.
GCI mode: The DOUT1 output is for clocking data out of GCI port 1. DCL1 is twice the
bit rate, that is, two clocks per data bit.
MOTOROLA
Chapter 19. Signal Descriptions
19-33