MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 328

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

PLIC Registers
13.5.21 Sync Delay Registers (P0SDR–P3SDR)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnSDR registers contain the frame sync delay bits for each of the four ports on the
MCF5272.
13.5.22 Clock Select Register (PCSR)
All bits in this register are read/write and are cleared on hardware or software reset.
PCSR controls the PLIC clock generation block. Please refer to Section 13.3, “PLIC
Timing Generator,” for certain restrictions on the use of the clock generation block.
13-32
15–14
13–10
Reset
Bits
9–0
Field FSW1 FSW0
Addr
R/W
FSW[1–0]
15
Name
SD
—
If a sync delay value of 0 is specified, that is,
PnSDR[SD] = 0x000, then the programmable delay block is
transparent. When bypassed, the input frame sync passes
directly to the output, making the frame-sync-width function
defined by PnSDR[FSW] unavailable.
The 8-bit frame-sync-width should not be confused with long
frame sync mode. The PLIC only supports short frame sync in
IDL8 and IDL10 bit modes for interfacing to external
transceivers.
14
Figure 13-33. Sync Delay Registers (P0SDR–P3SDR)
Frame sync width. Sets the width, in clock cycles, of the output frame sync pulse.
00 Frame sync width = 1
01 Frame sync width = 2
10 Frame sync width = 8
11 Frame sync width = 16
Reserved, should be cleared.
Sync delay. Range: 0–1023. Sets the delay, in DCL clock cycles, for DFSC3–DFSC0. The
delay period should be doubled in GCI mode because GCI has two clock cycles per data bit.
See Section 13.3, “PLIC Timing Generator,” for further information.
MBAR + 0x394 (P0SDR); 0x396 (P1SDR); 0x398 (P2SDR); 0x39A (P3SDR)
Table 13-16. P0SDR–P3SDR Field Descriptions
13
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MCF5272 User’s Manual
10
0000_0000_0000_0000
9
NOTE:
Read/Write
Description
SD
MOTOROLA
0