MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 297
![PROCESSOR MODULE FLASH MOD5272](/photos/6/75/67555/mod5272-100ir_sml.jpg)
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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Chapter 13
Physical Layer Interface Controller
(PLIC)
This chapter provides detailed information about the MCF5272’s physical layer interface
controller (PLIC), a module intended to support ISDN applications. The chapter begins
with a description of operation and a series of related block diagrams starting with a
high-level overview. Each successive diagram depicts progressively more internal detail.
The chapter then describes timing generation, the programming model, and concludes with
three application examples.
The reader is assumed to have a basic familiarity with ISDN technology and terminology.
A glossary containing many ISDN terms can be found on the web at the following URL:
http://www.tribecatech.com/isdnterm.htm.
13.1 Introduction
The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical
level with external CODECs (coder/decoder) and other peripheral devices that use either
the general circuit interface (GCI) or interchip digital link (IDL) physical layer protocols.
This module is primarily intended to facilitate designs that include ISDN (integrated
services digital network) interfaces.
The MCF5272 has four dedicated physical layer interface ports for connecting to external
ISDN transceivers, codecs, and other peripherals. There are three sets of pins for these
interfaces. Port 0 has its own dedicated set of pins. Ports 1, 2, and 3 share a set of pins.
Port 3 can also be configured to use a dedicated pin set. Ports 1, 2, and 3 always share the
same data clock (DCL).
When the ports are operated in slave mode, the PLIC can support a DCL frequency of
4.096 MHz and frame sync frequency (FSC/FSR) of 8 KHz. When in master mode, DCL
should be no greater than one-twentieth of the CPU clock (CLKIN), with a maximum
FSC/FSR of 8 KHz.
This chapter is written from the perspective of connecting to an ISDN transceiver with
8-KHz frame sync. The MCF5272 PLIC has four ports, port 0 – port 3, connected through
three pin sets, numbered 0, 1, and 3. A port can service, read, or write any 2B + D channel.
As shown in Figure 13-1, port 0 connects through pin set 0, and ports 1 and 2 both connect
MOTOROLA
Chapter 13. Physical Layer Interface Controller (PLIC)
13-1
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