MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 236

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Programming Model
11.5.1 Ethernet Control Register (ECR)
The ECR register, Figure 11-5, is used to enable/disable the FEC. It is written by the user
and cleared at system reset.
11.5.2 Interrupt Event Register (EIR)
An event that sets a bit in EIR generates an interrupt if the corresponding bit in the interrupt
mask register (EIMR) is set. Bits in the interrupt event register are cleared when a one is
written to them. Writing a zero has no effect.
11-12
31–26
24–2
Bits
25
1
0
Reset
Reset
Field
Field
Addr
R/W
R/W
ETHER_EN Ethernet enable. When this bit is set, the FEC is enabled, and reception and transmission is
RESET
31
15
TX_RT
Name
—
—
Reserved, should be cleared.
Transmit retime.
0 Normal operation, seven-wire serial mode.
1 The transmit output signals (E_TxD[3:0], E_TxEN, and E_TxER) are delayed by one-half
Reserved, should be cleared.
possible. When this bit is cleared, reception is immediately stopped and transmission is
stopped after a bad CRC is appended to any frame currently being transmitted. The buffer
descriptor(s) for an aborted transmit frame are not updated following deassertion of
ETHER_EN. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control
logic are reset, including FIFO pointers.
Ethernet controller reset. When this bit is set, the equivalent of a hardware reset is
performed but it is local to the FEC. ETHER_EN is cleared and all other FEC registers take
their reset values. Also, any transmission/reception currently in progress is abruptly aborted.
This bit is automatically cleared by hardware once the reset sequence is complete
(approximately 16 clock cycles after being set).
Figure 11-5. Ethernet Control Register (ECR)
of a E_TxCLK period. This bit should be set to provide compatibility with transceivers that
have hold time requirements that exceed the MII specification.
—
Table 11-7. ECR Field Descriptions
26
MCF5272 User’s Manual
TX_RT
25
—
0000_0000_0000_0000
0000_0000_0000_0000
24
MBAR + 0x840
Read/write
Read/write
Description
—
2
ETHER_EN RESET
1
MOTOROLA
16
0