MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 303

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
13.2.3.3 D-Channel HDLC Encoded Data
When the incoming D channels contain HDLC-encoded data, they are presented on the
physical line lsb first. The Soft HDLC expects the first bit received to be aligned in the lsb
position of a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb first, the
lsb is right-aligned in the transmit and receive shift register.
A D-channel byte is formed by concatenating two D bits from each of four frames. This
data is also right-aligned in the D-channel receive register as shown in Figure 13-7.
13.2.3.4 D-Channel Unencoded Data
As with the B channel, a mechanism is provided to support incoming D channels containing
unencoded data, even though as of this document’s publication date, no communication
protocols using unencoded D-channel data are known.
As with unencoded (PCM encoded) B-channel data, it is assumed unencoded D-channel
information is presented on the physical line msb first. The msb is left-aligned in the
transmit and receive shift register, that is, the first bit received is aligned in the msb position
through to the last received bit of a byte that is aligned in the lsb position.
A D-channel byte is formed by concatenating two D bits from each frame over four
consecutive frames as shown in Figure 13-7. These 8 bits are also left-aligned in the
DCL
FSR
Unencoded
HDLC
Encoded
Din/Dout
Din/Dout
Figure 13-7. D-Channel HDLC Encoded and Unencoded Data.
Frame 0
D
D
Chapter 13. Physical Layer Interface Controller (PLIC)
0
7
8-Bit D-Channel Receive/Transmit Register, RD, TD
Frame
D
D
1
6
D7
Frame 1
3
D6
D
D
2
5
D5
D
D
3
4
2
D4
D3
Frame 2
1
D2
D
D
4
3
D1
D
D
5
2
0
D0
Frame 3
D
D
6
1
D
D
7
0
GCI/IDL Block
13-7