MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 113

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
4.4.2.2 Programming ROMBAR for Power Management
Depending on the ROMBAR configuration, memory accesses can be sent to the ROM
module and the cache simultaneously. If an access hits both, the ROM module sources read
data and the instruction cache access is discarded. Because the ROM contains only for data,
setting ROMBAR[SC,UC] lowers power dissipation by disabling the ROM during
instruction fetches.
Table 4-5 shows typical ROMBAR settings:
RAMBAR can be configured similarly, as described in Section 4.3.2.3, “Programming
RAMBAR for Power Management.”
4.5 Instruction Cache Overview
The features of the instruction cache are as follows:
4.5.1 Instruction Cache Physical Organization
The instruction cache, Figure 4-3, is a direct-mapped single-cycle memory, organized as 64
lines, each containing 16 bytes. Memory consists of a 64-entry tag array (containing
addresses and a valid bit) and a 1-Kbyte instruction data array, organized as 64 x 128 bits.
The two memory arrays are accessed in parallel: bits 9–4 of the instruction fetch address
provide the index into the tag array; bits 9–2 address the data array. The tag array outputs
the address mapped to the given cache location along with the valid bit for the line. This
address field is compared to bits 31–10 of the instruction fetch address from the local bus
to determine if a cache hit in the memory array has occurred. If the desired address is
mapped into the cache memory, the output of the data array is driven onto the ColdFire
core's local data bus completing the access in a single cycle.
• 1-Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on ColdFire core's high-speed local bus
• Nonblocking design to maximize performance
• 16-byte line-fill buffer
• Configurable cache miss-fetch algorithm
Table 4-5. Examples of Typical ROMBAR Settings
Instructions only
Data only
Both instructions and data
Data Contained In ROM
Chapter 4. Local Memory
ROMBAR[7–0]
0x2B
0x35
0x21
Instruction Cache Overview
4-7