MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 70

PROCESSOR MODULE FLASH MOD5272

MOD5272-100IR

Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr

Specifications of MOD5272-100IR

Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
Features and Enhancements
2.1.1.1 Instruction Fetch Pipeline (IFP)
The IFP generates instruction addresses and fetches. Because the fetch and execution
pipelines are decoupled by a 3 longword FIFO buffer, the IFP can prefetch instructions
before the OEP needs them, minimizing stalls.
2-2
• Two-stage IFP (plus optional instruction buffer stage)
• Two-stage OEP
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction
— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the
— Address generation/execute (AGEX) calculates the operand address, or performs
bus.
fetch latency.
required components for the effective address calculation, or the operand fetch
cycle.
the execution of the instruction.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Instruction Buffer
Operand Fetch
Figure 2-1. ColdFire Pipeline
Generation,
Fetch Cycle
Instruction
Generation
Instruction
Address
Address
Execute
FIFO
MCF5272 User’s Manual
Address [31:0]
Data[31:0]
MOTOROLA

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