MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 77

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
Table 2-3 describes SR fields.
2.2.2.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement
of an exception vector is added to the value in this register to access the vector table.
VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be
aligned on a 0-modulo-1-Mbyte boundary.
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of both the instruction and data cache memory. It includes
bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining
the default cache mode and write-protect fields. See Section 4.5.3.1, “Cache Control
Register (CACR).”
Rc[11–0]
Reset
10–8
Field
Bits
R/W R/W
7–0
15
13
12
Reset
Field
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
Name
15
T
0
CCR
31
M
T
S
Exception vector table base address
I
—
R
0
Trace enable. When T is set, the processor performs a trace exception after every instruction.
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
Condition code register. See Table 2-4.
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
R/W
S
1
System Byte
R/W
M
0
Figure 2-6. Vector Base Register (VBR)
Table 2-3. Status Field Descriptions
Figure 2-5. Status Register (SR)
—
R
0
0000_0000_0000_0000_0000_0000_0000_0000
Chapter 2. ColdFire Core
20 19
R/W
111
I
8
0x801
Description
7
000
—
R
Condition Code Register (CCR)
—
R/W
—
X
R/W
—
N
Programming Model
R/W
—
Z
R/W
—
V
R/W
—
2-9
C
0
0