MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 247

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
Table 11-20 describes the RCR fields.
11.5.14 Maximum Frame Length Register (MFLR)
As shown in Figure 11-17, the MFLR register serves two purposes. Bits 10–0 provide the
user R/W MAX_FL field. The MAX_FL field allows the user to program the maximum
legal-size frame. Frames larger than this size cause the BABT interrupt (transmit frames)
or BABR interrupt and receive buffer descriptor LG bit to be asserted (receive frames).
Frames exceeding the MAX_FL are not truncated.
Bits 31–24 provide an eight-bit read-only field that provides address recognition
information from the receive block about the frame currently being received by the FEC.
Reset
Reset
Field
Field
Addr
R/W
R/W
31–4
Bits
3
2
1
0
31
15
MII_MODE
PROM
LOOP
Name
DRT
—
Figure 11-16. Receive Control Register (RCR)
Table 11-20. RCR Field Descriptions
Reserved, should be cleared.
Promiscuous mode. All frames are accepted regardless of address matching.
MII mode enable. Selects the external interface mode. Setting this bit to one
selects MII mode, setting this bit equal to zero selects seven-wire mode (used
only for serial 10 Mbps). This bit controls the interface mode for both transmit and
receive blocks.
Disable receive on transmit
0 Receive path operates independently of transmit (use for full duplex or to
monitor transmit activity in half-duplex mode).
1 Disable reception of frames while transmitting (normally used for half-duplex
mode).
Internal loopback. If set, transmitted frames are looped back internal to the FEC
and the transmit output signals are not asserted. The system clock is substituted
for the E_TxCLK when LOOP is asserted. DRT must be set to zero when
asserting LOOP.
Chapter 11. Ethernet Module
—
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x944
Read/Write
Read/Write
—
Description
4
PROM MII_MODE DRT LOOP
3
Programming Model
2
1
11-23
16
0