MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 476

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Bus Arbitration
20.11 Bus Arbitration
The MCF5272 does not allow external bus masters. There are three on-chip bus masters.
These are the ColdFire core, the Fast Ethernet Controller, and the memory-to-memory
DMA Controller.
20.12 Reset Operation
The MCF5272 supports four types of reset, two of which are external hardware resets
(master reset and normal reset), a soft reset, which is generated by setting SCR[SOFTRST],
and the software watchdog reset.
There are two reset input pins, RSTIRSTI and DRESETEN. When DRESETEN is asserted,
any of the reset sources reset the SDRAM controller. When DRESETEN is negated, the
SDRAM controller is not reset. This is useful during software debugging since it is
preferable to retain SDRAM data in the case of catastrophic system failure. In a production
system, if may be preferable to tie DRESETEN low.
Master reset resets the entire MCF5272 including the SDRAM controller. Master reset
occurs when both RSTI and DRESETEN are asserted simultaneously. This is the reset that
should be applied to the MCF5272 device at power up.
Normal reset resets all of the MCF5272 with the exception of the SDRAM controller.
Normal reset occurs when RSTI is asserted and DRESETEN is negated. Normal reset
allows DRAM refresh cycles to continue at the programmed rate and with the programmed
waveform timing while the remainder of the system is being reset, maintaining the data
stored in DRAM.
SCR[SOFTRST] resets all on-chip peripherals and devices connected to RSTO. It resets
the SDRAM controller only when DRESETEN is asserted.
The software watchdog reset acts as an internally generated normal reset when
DRESETEN is negated. It resets the SDRAM controller only when DRESETEN is
asserted.
20-22
TEA normally should be asserted for no more than three
CLKIN periods. The minimum is two clock periods.
TEA is internally synchronized on the rising edge of CLKIN.
Depending on when this synchronization takes place, the Cx
cycle may not occur.
MCF5272 User’s Manual
NOTE:
NOTE:
MOTOROLA