MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 109

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
4.3.2.1 SRAM Base Address Register (RAMBAR)
RAMBAR determines the base address location of the internal SRAM module, as well as
the definition of the types of accesses allowed for it.
RAMBAR fields are described in Table 4-2.
Address
31–12
11–9
Bits
7–6
Reset
8
• RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the
• The SRAM base address register (RAMBAR) can be accessed only in supervisor
Field
R/W
CPU address space via the MOVEC instruction with an Rc encoding of 0xC04.
RAMBAR can be read or written in background debug mode (BDM). At system
reset, the V bit is cleared and the remaining bits are uninitialized. To access the
SRAM module, RAMBAR must be written with the appropriate base address after
system reset.
mode using the MOVEC instruction with an Rc value of 0xC04.
Name
WP
31
BA
—
—
Base address. SRAM module base address. The SRAM module occupies a 4-Kbyte space
defined by BA. SRAM can reside on any 4-Kbyte boundary in the 4-Gbyte address space.
Reserved, should be cleared.
Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module.
1 Allows only read accesses to the SRAM module. Any attempted write reference generates an
Reserved, should be cleared.
access error exception to the ColdFire processor core.
Figure 4-1. SRAM Base Address Register (RAMBAR)
Table 4-2. RAMBAR Field Description
BA
Chapter 4. Local Memory
W for CPU; R/W for debug
CPU space + 0xC04
—
Description
12 11
—
9
WP
8
7
—
6
C/I SC SD UC UD V
5
4
SRAM Overview
3
2
1
4-3
0
0