LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 79

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 90.
UM10375
User manual
Name
IOCON_PIO1_11
IOCON_PIO3_2
IOCON_PIO1_5
IOCON_PIO1_6
IOCON_PIO1_7
IOCON_PIO3_3
IOCON_SCKLOC
Register overview: I/O configuration block (base address 0x4004 4000)
Table 91.
Port pin
PIO0_0
PIO0_1
PIO0_2
PIO0_3
PIO0_4
PIO0_5
PIO0_6
PIO0_7
PIO0_8
PIO0_9
IPIO0_10
PIO0_11
PIO1_0
IPIO1_1
IPIO1_2
PIO1_3
PIO1_4
PIO1_5
PIO1_6
PIO1_7
PIO1_8
PIO1_9
PIO1_10
PIO1_11
PIO2_0
PIO2_1
PIO2_2
PIO2_3
IPIO2_4
PIO2_5
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O configuration registers ordered by port number
Pin name
IOCON_RESET_PIO0_0
IOCON_PIO0_1
IOCON_PIO0_2
IOCON_PIO0_3
IOCON_PIO0_4
IOCON_PIO0_5
IOCON_PIO0_6
IOCON_PIO0_7
IOCON_PIO0_8
IOCON_PIO0_9
IOCON_SWCLK_PIO0_10
IOCON_R_PIO0_11
IOCON_R_PIO1_0
IOCON_R_PIO1_1
IOCON_R_PIO1_2
IOCON_SWDIO_PIO1_3
IOCON_PIO1_4
IOCON_PIO1_5
IOCON_PIO1_6
IOCON_PIO1_7
IOCON_PIO1_8
IOCON_PIO1_9
IOCON_PIO1_10
IOCON_PIO1_11
IOCON_PIO2_0
IOCON_PIO2_1
IOCON_PIO2_2
IOCON_PIO2_3
IOCON_PIO2_4
IOCON_PIO2_5
All information provided in this document is subject to legal disclaimers.
Address
offset
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
Rev. 2 — 7 July 2010
Description
I/O configuration for pin PIO1_11/AD7
I/O configuration for pin PIO3_2
I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0
I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0
I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1
I/O configuration for pin PIO3_3
SCK pin location select register
LQFP48
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Chapter 6: LPC13xx I/O configuration
…continued
HVQFN33
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UM10375
© NXP B.V. 2010. All rights reserved.
Reference
Table 94
Table 95
Table 97
Table 101
Table 102
Table 103
Table 109
Table 110
Table 114
Table 115
Table 116
Table 119
Table 120
Table 121
Table 122
Table 126
Table 127
Table 130
Table 131
Table 132
Table 96
Table 104
Table 117
Table 128
Table 93
Table 100
Table 113
Table 125
Table 106
Table 107
81 of 333
Reset
value
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0x00