LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 121

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
8.4.8 GPIO masked interrupt status register
8.4.9 GPIO interrupt clear register
Table 147. GPIOnIRS register (GPIO0IRS, address 0x5000 8014 to GPIO3IRS, address 0x5003
Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. GPIOMIS is the state of the
interrupt after masking. The register is read-only.
Table 148. GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address
This register allows software to clear edge detection for port bits that are identified as
edge-sensitive in the Interrupt Sense register. This register has no effect on port bits
identified as level-sensitive.
Table 149. GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
Bit
11:0
31:12
Bit
11:0
31:12
Bit
11:0
31:12
Symbol Value
RAWST
-
Symbol Value Description
MASK
-
Symbol
CLR
-
8014) bit description
0x5003 8018) bit description
801C) bit description
All information provided in this document is subject to legal disclaimers.
0
1
-
0
1
-
Value
0
1
-
Selects interrupt on pin x to be masked (x = 0 to 11).
No interrupt or interrupt masked on pin PIOn_x.
Interrupt on PIOn_x.
Reserved
Rev. 2 — 7 July 2010
Description
Raw interrupt status (x = 0 to 11).
No interrupt on pin PIOn_x.
Interrupt requirements met on PIOn_x.
Reserved
Description
Selects interrupt on pin x to be cleared (x = 0 to
11). Clears the interrupt edge detection logic. This
register is write-only.
Remark: The synchronizer between the GPIO and
the NVIC blocks causes a delay of 2 clocks. It is
recommended to add two NOPs after the clear of
the interrupt edge detection logic, before the exit of
the interrupt service routine.
No effect.
Clears edge detection logic for pin PIOn_x.
Reserved
Chapter 8: LPC13xx General Purpose I/O (GPIO)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0x00
-
Reset
value
0x00
-
0x00
Reset
value
-
W
-
Access
Access
R
-
123 of 333
Access
R
-