LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 196

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
UM10375
User manual
12.8.5.1 Selecting the appropriate I
12.8.5 I
Any of these registers which contain the bit 00x will be disabled and will not match any
address on the bus. The slave address register will be cleared to this disabled state on
reset. See also
Table 213. I
and I2C0SCLL- 0x4000 0014)
Table 214. I
Table 215. I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of I2C_PCLK cycles for the SCL
HIGH time, I2SCLL defines the number of I2C_PCLK cycles for the SCL low time. The
frequency is determined by the following formula (I2C_PCLK is the frequency of the
peripheral I2C clock):
The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate
I
gives some examples of I
I2SCLH values.
Bit
0
7:1
31:8 -
Bit
15:0
31:16
Bit
15:0
31:16
2
2
C data rate range. Each register value must be greater than or equal to 4.
C SCL HIGH and LOW duty cycle registers (I2C0SCLH - 0x4000 0010
Symbol Description
GC
Address The I
Symbol
SCLH
-
Symbol
SCLL
-
description
2
2
2
C Slave Address register 0 (I2C0ADR0- 0x4000 000C) bit description
C SCL HIGH Duty Cycle register (I2C0SCLH - address 0x4000 0010) bit
C SCL Low duty cycle register (I2C0SCLL - 0x4000 0014) bit description
General Call enable bit.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table
Description
Count for SCL HIGH time period selection.
Reserved. The value read from a reserved bit is not defined.
Description
Count for SCL low time period selection.
Reserved. The value read from a reserved bit is not defined.
2
C device address for slave mode.
219.
Rev. 2 — 7 July 2010
I 2 C
2
C-bus rates based on I2C_PCLK frequency and I2SCLL and
bitfrequency
2
C data rate and duty cycle
=
-------------------------------------------------------- -
I2CSCLH
Chapter 12: LPC13xx I2C-bus controller
I2CPCLK
+
I2CSCLL
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
0x00
-
Reset value
0x0004
-
Reset value
0x0004
-
Table 216
198 of 333
(4)

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