LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 328

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
12.8.8
12.8.9
12.8.10
12.9
12.9.1
12.9.2
12.9.3
12.9.4
12.10
12.10.1
12.10.2
12.10.3
12.10.4
12.10.5
12.10.6
12.10.7
12.10.8
12.10.9
12.10.10 Status decoder and status register . . . . . . . . 209
12.11
12.11.1
12.11.2
12.11.3
12.11.4
12.11.5
12.11.5.1 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 223
12.11.5.2 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 223
12.11.6
12.11.6.1 Simultaneous Repeated START conditions from
12.11.6.2 Data transfer after loss of arbitration . . . . . . 225
12.11.6.3 Forced access to the I
12.11.6.4 I
12.11.6.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
12.11.7
12.11.8
Chapter 13: LPC13xx SSP
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.7.1
13.7.2
13.7.3
UM10375
User manual
I
I
Details of I
How to read this chapter . . . . . . . . . . . . . . . . 235
Basic configuration . . . . . . . . . . . . . . . . . . . . 235
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
General description . . . . . . . . . . . . . . . . . . . . 235
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 236
Clocking and power control . . . . . . . . . . . . . 237
Register description . . . . . . . . . . . . . . . . . . . 237
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 202
C implementation and operation . . . . . . . . 205
I
0x4000 00[20, 24, 28]) . . . . . . . . . . . . . . . . . 201
I
0x4000 002C) . . . . . . . . . . . . . . . . . . . . . . . . 201
I
0x4000 00[30, 34, 38, 3C]) . . . . . . . . . . . . . . 202
Master Transmitter mode . . . . . . . . . . . . . . . 202
Master Receiver mode . . . . . . . . . . . . . . . . . 203
Slave Receiver mode . . . . . . . . . . . . . . . . . . 204
Slave Transmitter mode . . . . . . . . . . . . . . . . 205
Input filters and output stages. . . . . . . . . . . . 206
Address Registers, I2ADDR0 to I2ADDR3 . . 207
Address mask registers, I2MASK0 to
I2MASK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 207
Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 207
Arbitration and synchronization logic . . . . . . 207
Serial clock generator . . . . . . . . . . . . . . . . . . 208
Timing and control . . . . . . . . . . . . . . . . . . . . 209
Control register, I2CONSET and I2CONCLR 209
Master Transmitter mode . . . . . . . . . . . . . . . 210
Master Receiver mode . . . . . . . . . . . . . . . . . 214
Slave Receiver mode . . . . . . . . . . . . . . . . . . 217
Slave Transmitter mode . . . . . . . . . . . . . . . . 221
Miscellaneous states . . . . . . . . . . . . . . . . . . 223
Some special cases . . . . . . . . . . . . . . . . . . . 224
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 224
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
I
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SSP0 Control Register 0 (SSP0CR0 -
0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . 238
SSP0 Control Register 1 (SSP0CR1 -
0x4004 0004) . . . . . . . . . . . . . . . . . . . . . . . . 238
SSP0 Data Register (SSP0DR - 0x4004
0008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
2
2
2
2
2
C Slave Address registers (I2C0ADR[1, 2, 3]-
C Data buffer register (I2C0DATA_BUFFER -
C Mask registers (I2C0MASK[0, 1, 2, 3] -
C-bus obstructed by a LOW level on SCL or
C state service routines . . . . . . . . . . . . . . . 226
2
C operating modes. . . . . . . . . . . 209
2
C-bus . . . . . . . . . . . . 225
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
12.11.9
12.11.10 The state service routines . . . . . . . . . . . . . . 227
12.11.11 Adapting state services to an application. . . 227
12.12
12.12.1
12.12.2
12.12.3
12.12.4
12.12.5
12.12.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.12.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 228
12.12.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.12.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.12.6
12.12.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.12.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.12.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.12.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.12.6.5 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.12.7
12.12.7.1 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.12.7.2 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.12.7.3 State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.12.7.4 State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.12.8
12.12.8.1 State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.12.8.2 State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.12.8.3 State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.12.8.4 State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.12.8.5 State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.12.8.6 State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.12.8.7 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.12.8.8 State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.12.8.9 State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.12.9
12.12.9.1 State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.12.9.2 State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.12.9.3 State: 0xB8. . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.12.9.4 State: 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.12.9.5 State: 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 234
13.7.4
13.7.5
13.7.6
13.7.7
13.7.8
13.7.9
13.8
Chapter 21: LPC13xx Supplementary information
Software example . . . . . . . . . . . . . . . . . . . . . 227
Functional description . . . . . . . . . . . . . . . . . 242
I
Initialization routine . . . . . . . . . . . . . . . . . . . 227
Start Master Transmit function . . . . . . . . . . . 227
Start Master Receive function . . . . . . . . . . . 228
I
Non mode specific states. . . . . . . . . . . . . . . 228
Master Transmitter states . . . . . . . . . . . . . . 229
Master Receive states . . . . . . . . . . . . . . . . . 230
Slave Receiver states . . . . . . . . . . . . . . . . . 231
Slave Transmitter states . . . . . . . . . . . . . . . 233
SSP0 Status Register (SSP0SR - 0x4004
000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SSP0 Clock Prescale Register (SSP0CPSR -
0x4004 0010) . . . . . . . . . . . . . . . . . . . . . . . . 240
SSP0 Interrupt Mask Set/Clear Register
(SSP0IMSC - 0x4004 0014) . . . . . . . . . . . . 240
SSP0 Raw Interrupt Status Register (SSP0RIS -
0x4004 0018) . . . . . . . . . . . . . . . . . . . . . . . . 241
SSP0 Masked Interrupt Status Register
(SSP0MIS - 0x4004 001C) . . . . . . . . . . . . . 241
SSP0 Interrupt Clear Register (SSP0ICR -
0x4004 0020) . . . . . . . . . . . . . . . . . . . . . . . . 242
2
2
C interrupt service . . . . . . . . . . . . . . . . . . . 227
C interrupt routine . . . . . . . . . . . . . . . . . . . 228
UM10375
© NXP B.V. 2010. All rights reserved.
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