LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 282
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Price
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18.1 How to read this chapter
18.2 Basic configuration
18.3 Features
18.4 Pin description
UM10375
User manual
The ADC block is identical for all LPC13xx parts.
The ADC is configured using the following registers:
Table 277
Table 277. ADC pin description
The ADC function must be selected via the IOCON registers in order to get accurate
voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to
have a have a digital function selected and yet get valid ADC readings. An inside circuit
disconnects ADC hardware from the associated pin whenever a digital function is selected
on that pin.
Pin
AD[7:0]
V
1. Pins: The ADC pin functions are configured in the IOCONFIG register block
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 13
•
•
•
•
•
•
•
•
DD
UM10375
Chapter 18: LPC13xx Analog-to-Digital Converter (ADC)
Rev. 2 — 7 July 2010
(Section
Power to the ADC at run-time is controlled through the PDRUNCFG register
(Table
10-bit successive approximation Analog-to-Digital Converter (ADC).
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3.6 V. Do not exceed the V
10-bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
gives a brief summary of the ADC related pins.
52).
Type
Input
Input
6.4.1).
All information provided in this document is subject to legal disclaimers.
Description
Analog Inputs. The A/D converter cell can measure the voltage on any
of these input signals.
Remark: While the pins are 5 V tolerant in digital mode, the maximum
input voltage must not exceed V
analog inputs.
V
Rev. 2 — 7 July 2010
REF
; Reference voltage.
DD
when the pins are configured as
DD
voltage level.
© NXP B.V. 2010. All rights reserved.
User manual
(Table
284 of 333
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