LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 137

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
9.10.4.1 USB Device FIQ Select register (USBDevFIQSel - 0x4002 002C)
9.10.4 Miscellaneous registers
If the software makes the Read Enable bit low midway, the reading will be terminated. In
this case the data will remain in the RAM. When the Read Enable signal is made high
again for this endpoint, data will be read from the beginning.
For writing data to an endpoint buffer, the Write Enable bit should be made high and
software should write to the Tx Packet Length register the number of bytes it is going to
send in the packet. It can then write data continuously in the Transmit Data register. When
the control logic receives the number of bytes programmed in the Tx Packet length
register, it will reset the Write Enable bit. If the software resets this bit midway, writing will
start again from the beginning.
Both Read Enable and Write Enable bits can be high at the same time for the same logical
endpoint. The interleaved read and write operation is possible.
Remark: It takes 3 clock cycle to fetch the packet length from the RAM after programming
the USB control register. There can be a corruption on the packet length value read if the
reading of the packet length occurs immediately (in the very next clock cycle) after the
programming of USB control register. To avoid this problem, a NOP instruction has to be
inserted in between the programming of USBCtrl registers and reading of packet length
registers.
For example, follow these steps:
When a bit is set ‘1’, the corresponding interrupt will be routed to the high priority interrupt
line. Setting all bits to ‘1’ at the same time is not allowed. If the software attempts to set all
the bits to ‘1’, none of them will be routed to the high priority interrupt line.
Table 167. USB Device FIQ Select register (USBDevFIQSel - address 0x4002 002C) bit
Bit
0
1. USBCtrl = 0x01
2. delay(0) -- generate 1 clock cycle delay
3. pkt_length = USBTxPLen or USBRxPlen
Symbol
FRAME
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
Rev. 2 — 7 July 2010
Description
This interrupt comes from a 1 KHz free running clock
resynchronized on the incoming SoF tokens. This is to
be used for isochronous packet transfer.
FRAME interrupt will be routed to the low-priority
interrupt line IRQ.
FRAME interrupt will be routed to the high-priority
interrupt line FIQ.
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
139 of 333
Reset
value
0