LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 225
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
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12.12 Software example
UM10375
User manual
12.11.10 The state service routines
12.11.11 Adapting state services to an application
12.12.1 Initialization routine
12.12.2 Start Master Transmit function
12.11.8 Initialization
12.11.9 I
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
The I
Call. If the General Call or the own slave address is detected, an interrupt is requested
and I2STAT is loaded with the appropriate state information.
When the I
the 26 state services to be executed.
Each state routine is part of the I
The state service examples show the typical actions that must be performed in response
to the 26 I
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of timeout during I
operations, in order to trap an inoperative bus or a lost service routine.
Example to initialize I
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then
initiating a START.
2
1. Load I2ADR with own Slave Address, enable General Call recognition if needed.
2. Enable I
3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For
1. Initialize Master data counter.
•
•
•
C interrupt service
I2ADR is loaded with the part’s own slave address and the General Call bit (GC)
The I
The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON
and the serial clock frequency (for master modes) is defined by is defined by loading
the
program.
Master only functions, write 0x40 to I2CONSET.
2
C hardware now begins checking the I
I2SCLH and I2SCLL registers
2
2
C interrupt enable and interrupt priority bits are set
C state codes. If one or more of the four I
2
C interrupt is entered, I2STAT contains a status code which identifies one of
2
C interrupt.
All information provided in this document is subject to legal disclaimers.
2
C Interface as a Slave and/or Master.
Rev. 2 — 7 July 2010
2
2
C interrupt routine and handles one of the 26 states.
C block is enabled for both master and slave modes.
. The master routines must be started in the main
2
C-bus for its own slave address and General
Chapter 12: LPC13xx I2C-bus controller
2
C operating modes are not used, the
UM10375
© NXP B.V. 2010. All rights reserved.
2
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