LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 324

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
21.5 Contents
Chapter 1: LPC13xx Introductory information
1.1
1.2
1.3
Chapter 2: LPC13xx Memory mapping
2.1
2.2
Chapter 3: LPC13xx System configuration
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.5.14
3.5.15
3.5.16
3.5.17
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
3.5.28
3.5.29
3.5.30
3.5.31
3.5.32
3.5.33
UM10375
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
How to read this manual . . . . . . . . . . . . . . . . . . 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
How to read this chapter . . . . . . . . . . . . . . . . . . 8
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
How to read this chapter . . . . . . . . . . . . . . . . . 10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clocking and power control . . . . . . . . . . . . . . 12
Register description . . . . . . . . . . . . . . . . . . . . 13
Input pins to the start logic . . . . . . . . . . . . . . . .10
PIO reset status registers . . . . . . . . . . . . . . . . .10
USB clocking and power control. . . . . . . . . . . .10
System memory remap register . . . . . . . . . . . 15
Peripheral reset control register . . . . . . . . . . . 16
System PLL control register . . . . . . . . . . . . . . 16
System PLL status register. . . . . . . . . . . . . . . 17
USB PLL control register . . . . . . . . . . . . . . . . 17
USB PLL status register . . . . . . . . . . . . . . . . . 18
System oscillator control register . . . . . . . . . . 19
Watchdog oscillator control register . . . . . . . . 19
Internal resonant crystal control register. . . . . 20
System reset status register . . . . . . . . . . . . . . 21
System PLL clock source select register . . . . 21
System PLL clock source update enable
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
USB PLL clock source select register. . . . . . . 22
USB PLL clock source update enable register 23
Main clock source select register . . . . . . . . . . 23
Main clock source update enable register . . . 23
System AHB clock divider register . . . . . . . . . 24
System AHB clock control register . . . . . . . . . 24
SSP clock divider register. . . . . . . . . . . . . . . . 26
UART clock divider register . . . . . . . . . . . . . . 26
Trace clock divider register. . . . . . . . . . . . . . . 27
SYSTICK clock divider register. . . . . . . . . . . . 27
USB clock source select register . . . . . . . . . . 27
USB clock source update enable register. . . . 28
USB clock divider register. . . . . . . . . . . . . . . . 28
WDT clock source select register . . . . . . . . . . 28
WDT clock source update enable register . . . 29
WDT clock divider register . . . . . . . . . . . . . . . 29
CLKOUT clock source select register. . . . . . . 29
CLKOUT clock source update enable register 30
CLKOUT clock divider register . . . . . . . . . . . . 30
POR captured PIO status register 0 . . . . . . . . 31
POR captured PIO status register 1 . . . . . . . . 31
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
1.4
1.5
2.3
3.5.34
3.5.35
3.5.36
3.5.37
3.5.38
3.5.39
3.5.40
3.5.41
3.5.42
3.5.43
3.5.44
3.5.45
3.5.46
3.5.47
3.6
3.7
3.8
3.8.1
3.8.1.1
3.8.2
3.8.2.1
3.8.2.2
3.8.2.3
3.8.3
3.8.3.1
3.8.3.2
3.8.3.3
3.8.4
3.8.4.1
3.8.4.2
3.8.4.3
3.9
3.9.1
3.9.2
3.9.3
3.10
3.10.1
3.10.2
3.10.3
Chapter 21: LPC13xx Supplementary information
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory remapping . . . . . . . . . . . . . . . . . . . . . . 9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Brown-out detection . . . . . . . . . . . . . . . . . . . . 42
Power management . . . . . . . . . . . . . . . . . . . . 42
Deep-sleep mode details . . . . . . . . . . . . . . . . 46
PLL (System PLL and USB PLL) functional
description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
BOD control register . . . . . . . . . . . . . . . . . . . 31
System tick counter calibration register . . . . . 32
Start logic edge control register 0 . . . . . . . . . 32
Start logic signal enable register 0 . . . . . . . . . 33
Start logic reset register 0 . . . . . . . . . . . . . . . 34
Start logic status register 0 . . . . . . . . . . . . . . 34
Start logic edge control register 1 . . . . . . . . . 35
Start logic signal enable register 1 . . . . . . . . . 36
Start logic reset register 1 . . . . . . . . . . . . . . . 36
Start logic status register 1 . . . . . . . . . . . . . . 37
Deep-sleep mode configuration register . . . . 38
Wake-up configuration register . . . . . . . . . . . 39
Power-down configuration register . . . . . . . . 40
Device ID register . . . . . . . . . . . . . . . . . . . . . 41
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power configuration in Active mode. . . . . . . . 43
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power configuration in Sleep mode . . . . . . . . 43
Programming Sleep mode . . . . . . . . . . . . . . . 43
Wake-up from Sleep mode . . . . . . . . . . . . . . 43
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 44
Power configuration in Deep-sleep mode . . . 44
Programming Deep-sleep mode . . . . . . . . . . 44
Wake-up from Deep-sleep mode . . . . . . . . . . 45
Deep power-down mode . . . . . . . . . . . . . . . . 45
Power configuration in Deep power-down
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Programming Deep power-down mode . . . . . 45
Wake-up from Deep power-down mode . . . . 46
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 46
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Using the general purpose counter/timers to
create a self-wake-up event. . . . . . . . . . . . . . 46
Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power-down control . . . . . . . . . . . . . . . . . . . . 48
Divider ratio programming . . . . . . . . . . . . . . . 48
UM10375
© NXP B.V. 2010. All rights reserved.
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