LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 265
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
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LPC1313FBD48,151
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Table 260: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
UM10375
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
31:12
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
-
bit description
15.8.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Feature disabled.
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Feature disabled.
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Feature disabled.
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table
260.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 15: LPC13xx 32-bit timer/counters (CT32B0/1)
UM10375
© NXP B.V. 2010. All rights reserved.
267 of 333
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
NA
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