LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 176

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
Fig 17. Auto-CTS Functional Timing
UART TX
CTS pin
11.6.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)
start
bits0..7
While starting transmission of the initial character, the CTS signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets
de-asserted, transmission resumes and a start bit is sent followed by the data bits of the
next character.
The U0LSR is a Read Only register that provides status information on the UART TX and
RX blocks.
Table 198. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
Bit Symbol
0
1
2
Receiver
Data
Ready
(RDR)
Overrun
Error
Parity
Error
(OE)
(PE)
stop
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
U0LSR[0] is set when the U0RBR holds an unread character and
is cleared when the UART RBR FIFO is empty.
U0RBR is empty.
U0RBR contains valid data.
The overrun error condition is set as soon as it occurs. A U0LSR
read clears U0LSR[1]. U0LSR[1] is set when UART RSR has a
new character assembled and the UART RBR FIFO is full. In this
case, the UART RBR FIFO will not be overwritten and the
character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
When the parity bit of a received character is in the wrong state, a
parity error occurs. A U0LSR read clears U0LSR[2]. Time of
parity error detection is dependent on U0FCR[0].
Note: A parity error is associated with the character at the top of
the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
Rev. 2 — 7 July 2010
start
bits0..7
stop
Chapter 11: LPC13xx UART
start
UM10375
© NXP B.V. 2010. All rights reserved.
bits0..7
178 of 333
stop
Reset
Value
0
0
0