LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 78

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 90.
UM10375
User manual
Name
IOCON_PIO0_1
IOCON_PIO1_8
-
IOCON_PIO0_2
IOCON_PIO2_7
IOCON_PIO2_8
IOCON_PIO2_1
IOCON_PIO0_3
IOCON_PIO0_4
IOCON_PIO0_5
IOCON_PIO1_9
IOCON_PIO3_4
IOCON_PIO2_4
IOCON_PIO2_5
IOCON_PIO3_5
IOCON_PIO0_6
IOCON_PIO0_7
IOCON_PIO2_9
IOCON_PIO2_10
IOCON_PIO2_2
IOCON_PIO0_8
IOCON_PIO0_9
IOCON_SWCLK_PIO0_10
IOCON_PIO1_10
IOCON_PIO2_11
IOCON_R_PIO0_11
IOCON_R_PIO1_0
IOCON_R_PIO1_1
IOCON_R_PIO1_2
IOCON_PIO3_0
IOCON_PIO3_1
IOCON_PIO2_3
IOCON_SWDIO_PIO1_3
IOCON_PIO1_4
Register overview: I/O configuration block (base address 0x4004 4000)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Address
offset
0x014
0x018
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x050
0x054
0x058
0x05C
0x060
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x094
0x010
0x01C
0x04C
0x064
0x090
Rev. 2 — 7 July 2010
I/O configuration for pin PIO3_1
I/O configuration for pin PIO2_3/RI
Description
I/O configuration for pin PIO0_1/CLKOUT/
CT32B0_MAT2/USB_FTOGGLE
I/O configuration for pin PIO1_8/CT16B1_CAP0
Reserved
I/O configuration for pin PIO0_2/SSEL/
CT16B0_CAP0
I/O configuration for pin PIO2_7
I/O configuration for pin PIO2_8
I/O configuration for pin PIO2_1/DSR
I/O configuration for pin PIO0_3/USB_VBUS
I/O configuration for pin PIO0_4/SCL
I/O configuration for pin PIO0_5/SDA
I/O configuration for pin PIO1_9/CT16B1_MAT0
I/O configuration for pin PIO3_4
I/O configuration for pin PIO2_4
I/O configuration for pin PIO2_5
I/O configuration for pin PIO3_5
I/O configuration for pin PIO0_6/USB_CONNECT/SCK
I/O configuration for pin PIO0_7/CTS
I/O configuration for pin PIO2_9
I/O configuration for pin PIO2_10
I/O configuration for pin PIO2_2/DCD
I/O configuration for pin PIO0_8/MISO/CT16B0_MAT0
I/O configuration for pin PIO0_9/MOSI/
CT16B0_MAT1/SWO
I/O configuration for pin SWCLK/PIO0_10/
SCK/CT16B0_MAT2
I/O configuration for pin PIO1_10/AD6/
CT16B1_MAT1
I/O configuration for pin PIO2_11/SCK
I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3
I/O configuration for pin R/PIO1_0/AD1/
CT32B1_CAP0
I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0
I/O configuration for pin R/PIO1_2/AD3/
CT32B1_MAT1
I/O configuration for pin PIO3_0
I/O configuration for pin SWDIO/PIO1_3/AD4/
CT32B1_MAT2
I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3
Chapter 6: LPC13xx I/O configuration
…continued
UM10375
© NXP B.V. 2010. All rights reserved.
80 of 333
Reset
value
0xD0
0xD0
-
0xD0
0xD0
0xD0
0xD0
0xD0
0x00
0x00
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0
0xD0