LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 126

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
9.6 General description
UM10375
User manual
Fig 12. USB device controller block diagram
(APB slave)
9.6.1 Analog transceiver
9.6.2 Serial Interface Engine (SIE)
9.6.3 Endpoint RAM (EP_RAM)
9.6.4 EP_RAM access control
interface
register
USB DEVICE
BLOCK
The architecture of the USB device controller is shown below in
The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bi-directional USB_DP and USB_DM signals of the USB bus.
The SIE implements the full USB protocol layer. It is completely hardwired for speed and
needs no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.
Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for
this purpose is called the EP_RAM. Each endpoint has a reserved space in the EP_RAM.
The total EP_RAM space is fixed. All endpoints are realized automatically.
The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the
sources that can access it: the CPU (via the Register Interface) and the SIE.
INTERFACE
MASTER
INTERFACE
REGISTER
BUS
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
CONTROL
EP_RAM
ACCESS
INTERFACE
ENGINE
SERIAL
Chapter 9: LPC13xx USB device controller
Figure
UM10375
© NXP B.V. 2010. All rights reserved.
USB_DP
USB_DM
12.
V
USB_CONNECT
BUS
128 of 333