LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 151

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The following example illustrates how double-buffering works for a Bulk IN endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.
3. Software is still reading from B_1 when the host attempts to send a third packet. Since
4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer
5. Software sends the SIE Select Endpoint command to read the Select Endpoint
6. The host resends the third packet which device hardware places in B_1. An endpoint
7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
1. The host requests a data packet by sending an IN token packet. The device responds
2. Software clears the endpoint interrupt. The device has three packets to send.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and
7. The device successfully sends the second packet from B_2 and generates an
8. Software has no more packets to send, so it simply clears the interrupt.
both B_1 and B_2 are full, the device hardware responds with a NAK.
command to free B_1 to receive another packet. B_2 becomes the active buffer.
Register and test the FE bit. Software finds that the active buffer (B_2) has data
(FE=1). Software clears the endpoint interrupt and begins reading the contents of
B_2.
interrupt is generated.
command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
packet from B_1.
command to free B_1 to receive another packet. B_2 becomes the active buffer.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.
with a NAK and generates an endpoint interrupt.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the
second packet. Software sends a SIE Validate Buffer command, and the active buffer
is switched to B_1.
interrupt occurs.
validates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
endpoint interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
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