LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 34

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
3.5.40 Start logic edge control register 1
Table 44.
The STARTAPRP1 register controls the start logic inputs of ports 2 (PIO2_8 to PIO2_11)
and 3 (PIO3_0 to PIO3_3). This register selects a falling or rising edge on the
corresponding PIO input to produce a falling or rising clock edge, respectively, for the
start-up logic.
Every bit in the STARTAPRP1 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP1 register corresponds to interrupt
32, bit 1 to interrupt 33, up to bit 7 corresponding to interrupt 39 (see
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
Table 45.
Bit
0
11:1
12
23:13
24
31:25
Bit
0
Symbol
APRPIO2_8
Symbol
SRPIO0_0
SRPIO0_11 to
SRPIO0_1
SRPIO1_0
SRPIO1_11 to
SRPIO1_1
SRPIO2_0
SRPIO2_7 to
SRPIO2_1
Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Start logic edge control register 1 (STARTAPRP1, address 0x4004 8210) bit
description
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Value
0
1
Value
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 2 — 7 July 2010
Description
Edge select for start logic input PIO2_8
Falling edge
Rising edge
Description
Start signal status for start logic input PIO0_0
No start signal received
Start signal pending
Start signal status for start logic input PIO0_11 to
PIO0_1
No start signal received
Start signal pending
Start signal status for start logic input PIO1_0
No start signal received
Start signal pending
Start signal status for start logic input PIO1_11 to
PIO1_1
No start signal received
Start signal pending
Start signal status for start logic input PIO2_0
No start signal received
Start signal pending
Start signal status for start logic input PIO2_7 to
PIO2_1
No start signal received
Start signal pending
Chapter 3: LPC13xx System configuration
Table
UM10375
© NXP B.V. 2010. All rights reserved.
61).
Reset
value
n/a
n/a
n/a
n/a
n/a
n/a
Reset
value
0
35 of 333