LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 150

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
9.14 Double-buffered endpoint operation
UM10375
User manual
9.13.5 Automatic stall feature
9.14.1 Bulk endpoints
It is assumed that the Isochronous pipe is open at the reception of a request "Set Interface
(alternate setting > 0)". This request is sent to the interface to which the isochronous
endpoint belongs.
This means that the device is expecting the first isochronous transfer within the
millisecond.
The USB block includes a Hardware STALL mechanism. H/W STALL will occur in
the following control transactions:
A STALL will not occur in the following situations:
The Bulk and Isochronous endpoints of the USB Device Controller are double-buffered to
increase data throughput.
For the following discussion, the endpoint buffer currently accessible to the CPU for
reading or writing is said to be the active buffer.
For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or
Validate Buffer commands.
The following example illustrates how double-buffering works for a Bulk OUT endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is
B_1.
1. The host sends a data packet to the endpoint. The device hardware puts the packet
2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
•
•
•
•
•
Data stage consists of INs, the status is a single OUT transaction with an empty
packet sent by the host.
Data stage consists of OUTs, the status is a single IN transaction, for which the device
respond with an empty packet.
Setup stage followed by a Status stage consisting of an IN transaction, for which the
device respond with empty packet.
Data stage consists of OUTs, the status is a single IN transaction, for which the device
respond with a non-empty packet.
Setup stage followed by a Status stage consisting of an IN transaction, for which the
device respond with a non-empty packet.
into B_1, and generates an endpoint interrupt.
While B_1 is still being read, the host sends a second packet, which device hardware
places in B_2, and generates an endpoint interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
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