LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 262

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 256. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000)
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UM10375
User manual
Name
TMR32B0IR
TMR32B0TCR
TMR32B0TC
TMR32B0PR
TMR32B0PC
TMR32B0MCR
TMR32B0MR0
TMR32B0MR1
TMR32B0MR2
TMR32B0MR3
TMR32B0CCR
TMR32B0CR0
TMR32B0EMR
-
TMR32B0CTCR
TMR32B0PWMC R/W
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
-
R/W
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x03C
0x040 -
0x06C
0x070
0x074
Description
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
Prescale Counter (PC). The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
Match Register 1 (MR1). See MR0 description.
Match Register 2 (MR2). See MR0 description.
Match Register 3 (MR3). See MR0 description.
Capture Control Register (CCR). The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or
not an interrupt is generated when a capture takes place.
Capture Register 0 (CR0). CR0 is loaded with the value of TC when
there is an event on the CT32B0_CAP0 input.
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B0_MAT[3:0].
reserved
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B0_MAT[3:0].
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 15: LPC13xx 32-bit timer/counters (CT32B0/1)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
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