LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 204

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
Fig 27. I
2
C serial interface block diagram
12.10.1 Input filters and output stages
SDA
SCL
status
bus
Input signals are synchronized with the internal clock, and spikes shorter than three
clocks are filtered out.
The output for I
OUTPUT
OUTPUT
FILTER
FILTER
STAGE
INPUT
STAGE
INPUT
DECODER
STATUS
2
All information provided in this document is subject to legal disclaimers.
C is a special pad designed to conform to the I
I2CnADDR0 to I2CnADDR3
ADDRESS REGISTERS
I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL
MASK and COMPARE
ARBITRATION and
MONITOR MODE
SERIAL CLOCK
BIT COUNTER/
I2CnMMCTRL
GENERATOR
Rev. 2 — 7 July 2010
SYNC LOGIC
REGISTER
SCL DUTY CYLE REGISTERS
SHIFT REGISTER
CONTROL REGISTER and
STATUS REGISTER
I2CnDAT
I2CnSTAT
MATCHALL
I2CnMMCTRL[3]
I2CnMASK0 to I2CnMASK3
TIMING and
CONTROL
LOGIC
Chapter 12: LPC13xx I2C-bus controller
MASK REGISTERS
I2CnDATABUFFER
ACK
PCLK
interrupt
16
8
8
8
2
C specification.
UM10375
© NXP B.V. 2010. All rights reserved.
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