LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 238

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
13.7.5 SSP0 Clock Prescale Register (SSP0CPSR - 0x4004 0010)
13.7.6 SSP0 Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4004 0014)
Table 238: SSP0 Status Register (SSP0SR - address 0x4004 000C bit description
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
SSP0CR0, to determine the bit clock.
Table 239: SSP0 Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit description
Important: the SSP0CPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in
relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
31:5
Bit
7:0
31:8
Symbol
TFE
TNF
RNE
RFF
BSY
-
Symbol
CPSDVSR This even value between 2 and 254, by which SSP_PCLK is
-
All information provided in this document is subject to legal disclaimers.
Description
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
min
= 2 or larger (even numbers only).
Table
24. The content of the SSP0CPSR register is not
Chapter 13: LPC13xx SSP
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
NA
Reset value
1
0
0
0
NA
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