LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 293

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
19.9.1 Usage note
directory, thereby updating the user code in flash. Note that the filename of the new flash
image file is not important. After a reset or a power cycle, the new file is visible in the
host’s file system under it’s default name ‘firmware.bin’.
Remark: USB ISP commands are supported for Windows operating system only.
The code read protection (CRP, see
reprogrammed:
Remark: The only Windows commands supported for the LPC134x flash image folder are
copy and delete.
Three Code Read Protection (CRP) levels can be enabled for flash images updated
through USB (see
CRP status.
Table 286. CRP levels for USB boot images
When programming flash images via Flash Magic or Serial Wire Debugger (SWD), the
user code valid signature is automatically inserted by the programming utility. When using
USB ISP, the user code valid signature must be either part of the vector table, or the axf or
binary file must be post-processed to insert the checksum.
CRP status Volume label
No CRP
CRP1
CRP2
CRP3
If CRP2 or CRP3 is enabled, the user flash is erased when the file is deleted.
If CRP1 is enabled or no CRP is selected, the user flash is erased and reprogrammed
when the new file is copied. However, only the area occupied by the new file is erased
and reprogrammed.
CRP DISABLD
CRP1 ENABLD
CRP2 ENABLD
CRP3 ENABLD
All information provided in this document is subject to legal disclaimers.
Section 19.12
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
Description
The user flash can be read or written.
The user flash content cannot be read but can be updated. The
flash memory sectors are updated depending on the new
firmware image.
The user flash content cannot be read but can be updated. The
entire user flash memory is erased before writing the new
firmware image.
The user flash content cannot be read or updated. The
bootloader always executes the user application if valid.
for details). The volume label on the MSCD indicates the
Table
286) level determines how the flash is
UM10375
© NXP B.V. 2010. All rights reserved.
295 of 333