LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 120

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
UM10375
User manual
8.4.4 GPIO interrupt both edges sense register
8.4.5 GPIO interrupt event register
8.4.6 GPIO interrupt mask register
8.4.7 GPIO raw interrupt status register
Table 144. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003
Table 145. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003
Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their
individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt
triggering on that pin.
Table 146. GPIOnIE register (GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003
Bits read HIGH in the GPIOnIRS register reflect the raw (prior to masking) interrupt status
of the corresponding pins indicating that all the requirements have been met before they
are allowed to trigger the GPIOIE. Bits read as zero indicate that the corresponding input
pins have not initiated an interrupt. The register is read-only.
Bit
11:0
31:12
Bit
11:0
31:12
Bit
11:0
31:12
Symbol Value
IBE
-
Symbol
IEV
-
Symbol Value Description
MASK
-
8008) bit description
800C) bit description
8010) bit description
All information provided in this document is subject to legal disclaimers.
0
1
-
0
1
-
Value
0
1
-
Selects interrupt on pin x to be masked (x = 0 to 11). 0x00
Interrupt on pin PIOn_x is masked.
Interrupt on pin PIOn_x is not masked.
Reserved
Description
Selects interrupt on pin x to be triggered on both
edges (x = 0 to 11).
Interrupt on pin PIOn_x is controlled through register
GPIOnIEV.
Both edges on pin PIOn_x trigger an interrupt.
Reserved
Rev. 2 — 7 July 2010
Description
Selects interrupt on pin x to be triggered rising or
falling edges (x = 0 to 11).
Depending on setting in register GPIOnIS (see
Table
PIOn_x trigger an interrupt.
Depending on setting in register GPIOnIS (see
Table
PIOn_x trigger an interrupt.
Reserved
143), falling edges or LOW level on pin
143), rising edges or HIGH level on pin
Chapter 8: LPC13xx General Purpose I/O (GPIO)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0x00
-
Reset
value
-
Reset
value
0x00
-
Access
R/W
-
Access
R/W
-
Access
R/W
-
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