LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 45

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
3.9 Deep-sleep mode details
UM10375
User manual
3.8.4.3 Wake-up from Deep power-down mode
3.9.1 IRC oscillator
3.9.2 Start logic
3.9.3 Using the general purpose counter/timers to create a self-wake-up
Pulling the WAKEUP pin LOW wakes up the LPC13xx from Deep power-down, and the
chip goes through the entire reset process
Remark: The RESET pin has no functionality in Deep power-down mode.
The IRC is the only oscillator on the LPC13xx that can always shut down glitch-free.
Therefore it is recommended that the user switches the clock source to IRC before the
chip enters Deep-sleep mode.
The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM
core. The various port pins (see
wake-up pins. The user must program the start logic registers for each input to set the
appropriate edge polarity for the corresponding wake-up event. Furthermore, the
interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 39 in
the NVIC correspond to 40 PIO pins (see
The start logic does not require a clock to run because it uses the input signals on the
enabled pins to generate a clock edge when enabled. Therefore, the start logic signals
should be cleared (see
The start logic can also be used in Active mode to provide a vectored interrupt using the
LPC13xx’s input pins.
event
If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers
can count clock cycles of the watchdog oscillator and create a match event when the
number of cycles equals a preset match value. The match event causes the
corresponding match output pin to go HIGH, LOW, or toggle. The state of the match
1. On the WAKEUP pin, transition from HIGH to LOW.
2. Once the chip has booted, read the deep power-down flag in the PCON register
3. Clear the deep power-down flag in the PCON register
4. (Optional) Read the stored data in the general purpose registers
5. Set up the PMU for the next Deep power-down cycle.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
– All registers except the GPREG0 to GPREG4and PCON will be in their reset state.
(Table
power-down and was not a cold reset.
Table
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
60).
58) to verify that the reset was caused by a wake-up event from Deep
All information provided in this document is subject to legal disclaimers.
Table 43
Rev. 2 — 7 July 2010
Table
and
Table
4) are connected to the start logic and serve as
Section 3.5.36
(Section
47) before use.
Chapter 3: LPC13xx System configuration
3.6).
and
(Table
Section
58).
(Table 59
3.5.40).
UM10375
© NXP B.V. 2010. All rights reserved.
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