LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 117

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

8.1 How to read this chapter
Table 138. GPIO configuration
8.2 Features
8.3 Pin description
8.4 Register description
UM10375
User manual
Part
LPC1311
LPC1313 LQFP48
LPC1313 HVQFN33
LPC1342 HVQFN33
LPC1343 LQFP48
Package
HVQFN33
HVQFN33
The number of GPIO pins available on each port depends on the LPC13xx part and the
package. See
GPIO port 0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
Table 139. GPIO pin description
[1]
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
Pin
PIO0_0 to PIO0_11
PIO1_0 to PIO1_11
PIO2_0 to PIO2_11
PIO3_0 to PIO3_11
•
•
•
•
•
•
UM10375
Chapter 8: LPC13xx General Purpose I/O (GPIO)
Rev. 2 — 7 July 2010
GPIO pins can be configured as input or output by software.
Each individual port pin can serve as an edge- or level-sensitive interrupt request.
Interrupts can be configured on single falling or rising edges and on both edges.
Level-sensitive interrupt pins can be HIGH- or LOW-active.
All GPIO pins are inputs by default.
Reading and writing of data registers are masked by address bits 13:2.
The pin configuration depends on the LPC13xx package (see
Table 138
All information provided in this document is subject to legal disclaimers.
GPIO port 1
Rev. 2 — 7 July 2010
for available GPIO pins:
I/O
I/O
I/O
I/O
Type
[1]
Description
GPIO port 0 input/output pins.
GPIO port 1 input/output pins.
GPIO port 2 input/output pins.
GPIO port 3 input/output pins.
GPIO port 2
Table
GPIO port 3
PIO3_2; PIO3_4; PIO3_5 28
PIO3_2; PIO3_4; PIO3_5 28
PIO3_2
PIO3_2
138).
© NXP B.V. 2010. All rights reserved.
User manual
119 of 333
Total
GPIO
pins
42
26
40
26