LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 149

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
9.13.2 Data flow from the Device to the Host
9.13.3 Interrupt based transfer
9.13.4 Isochronous transfer
Isochronous endpoint will have one packet of data to be transferred in every frame. This
requires the data transfer has to be synchronized to the USB frame rather than packet
arrival. The 1 KHz free running clock re synchronized on the incoming SoF tokens will
generate an interrupt every millisecond.
The data transfer follows the little endian format. The first byte received from the USB bus
will be available in the LS byte of the receive data register.
For data transfer from an endpoint to the host, the host will send an IN token to that
endpoint. If the FIFO corresponding to the endpoint is empty, the device will return a NAK
and will generate an interrupt (assuming the interrupt on NAK is enabled). On this
interrupt the processor fills a packet of data in the endpoint FIFO. The next IN token that
comes--after filling this packet--will transfer this packet to the host.
The data transfer follows the little endian format. The first byte sent on the USB bus will be
the LS byte of the transmit data register.
Remark: USB is a host controlled protocol, i.e., irrespective of whether the data transfer is
from the host to the device or from the device to the host, the transfer sequence is always
initiated by the host. During data transfer from the device to the host, the host sends an IN
token to the device, following which the device responds with the data.
Interrupt based data transfer is done through the interrupt issued from the USB core to the
processor.
Reception of a valid (error-free) data packet in any of the OUT non-isochronous endpoint
buffer generates an interrupt. Upon receiving the interrupt, the software can read the data
using receive length and data registers. When there is no empty buffer (for a given
non-isochronous OUT endpoint), any data arrival generates an interrupt only if Interrupt
On NAK feature for that endpoint type is enabled and existing interrupt is cleared.
Similarly, when a packet is successfully transferred to the host from any IN
non-isochronous endpoint buffer, an interrupt is generated. When there is no data
available in any of the buffers (for a given non-isochronous IN endpoint), a data request
generates an interrupt only if Interrupt On NAK feature for that endpoint type is enabled
and existing interrupt is cleared. Upon receiving the interrupt, the software can load any
data to be sent using transmit length and data registers.
Isochronous endpoints are double-buffered and the buffer toggling will happen only on
frame boundaries i.e., at every 1 ms. ‘Clear Buffer’ and ‘Validate Buffer’ do not cause the
buffer to toggle.
For OUT isochronous endpoints, the data will always be written irrespective of the buffer
status. For IN isochronous endpoints, the data available in the buffer will be sent only if the
buffer is validated; otherwise, an empty packet will be sent.
There will not be any interrupt generated specific to isochronous endpoints other than the
frame interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
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