LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 177
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
MAXIM
Quantity:
1 560
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
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UM10375
User manual
11.6.10 UART Modem Status Register
Table 198. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
The U0MSR is a read-only register that provides status information on the modem input
signals. U0MSR[3:0] is cleared on U0MSR read. Note that modem signals have no direct
effect on the UART operation. They facilitate the software implementation of modem
signal operations.
Bit Symbol
3
4
5
6
7
31:
8
Framing
Error
Break
Interrupt
Transmitte
r Holding
Register
Empty
Transmitte
r Empty
(TEMT)
Error in RX
FIFO
(RXFE)
-
(FE)
(BI)
(THRE)
description
All information provided in this document is subject to legal disclaimers.
Value Description
-
0
1
0
1
0
1
0
1
0
1
…continued
When the stop bit of a received character is a logic 0, a framing
error occurs. A U0LSR read clears U0LSR[3]. The time of the
framing error detection is dependent on U0FCR0. Upon detection
of a framing error, the RX will attempt to re-synchronize to the
data and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will be
correct even if there is no Framing Error.
Note: A framing error is associated with the character at the top
of the UART RBR FIFO.
Framing error status is inactive.
Framing error status is active.
When RXD1 is held in the spacing state (all zeros) for one full
character transmission (start, data, parity, stop), a break interrupt
occurs. Once the break condition has been detected, the receiver
goes idle until RXD1 goes to marking state (all ones). A U0LSR
read clears this status bit. The time of break detection is
dependent on U0FCR[0].
Note: The break interrupt is associated with the character at the
top of the UART RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
THRE is set immediately upon detection of an empty UART THR
and is cleared on a U0THR write.
U0THR contains valid data.
U0THR is empty.
TEMT is set when both U0THR and U0TSR are empty; TEMT is
cleared when either the U0TSR or the U0THR contain valid data.
U0THR and/or the U0TSR contains valid data.
U0THR and the U0TSR are empty.
U0LSR[7] is set when a character with a RX error such as framing
error, parity error or break interrupt, is loaded into the U0RBR.
This bit is cleared when the U0LSR register is read and there are
no subsequent errors in the UART FIFO.
U0RBR contains no UART RX errors or U0FCR[0]=0.
UART RBR contains at least one UART RX error.
Reserved
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
179 of 333
Reset
Value
0
0
1
1
0
-
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