LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 292

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
19.9 USB communication protocol
UM10375
User manual
19.8.4 ISP flow control
19.8.5 ISP command abort
19.8.6 Interrupts during ISP
19.8.7 Interrupts during IAP
19.8.8 RAM used by ISP command handler
19.8.9 RAM used by IAP command handler
The receiver should compare it with the check-sum of the received bytes. If the
check-sum matches then the receiver should respond with "OK<CR><LF>" to continue
further transmission. If the check-sum does not match the receiver should respond with
"RESEND<CR><LF>". In response the sender should retransmit the bytes.
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to
stop the flow of data. Data flow is resumed by sending the ASCII control character DC1
(start). The host should also support the same flow control scheme.
Commands can be aborted by sending the ASCII control character "ESC". This feature is
not documented as a command under "ISP Commands" section. Once the escape code is
received the ISP command handler waits for a new command.
The boot block interrupt vectors located in the boot block of the flash are active after any
reset.
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing, the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.
ISP commands use on-chip RAM from 0x1000 017C to 0x1000 025B. The user could use
this area, but the contents may be lost upon reset. Flash programming commands use the
top 32 bytes of on-chip RAM. The stack is located at RAM top − 32 bytes. The maximum
stack usage is 256 bytes and grows downwards.
Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stack
usage in the user allocated stack space is 128 bytes and grows downwards.
The LPC134x is enumerated as a Mass Storage Class (MSC) device to a PC or another
embedded system. In order to connect via the USB interface, the LPC134x must use the
external crystal at a frequency of 12 MHz. The MSC device presents an easy integration
with the PC’s Windows operating system. The LPC134x flash memory space is
represented as a drive in the host file system. The entire available user flash is mapped to
a file of the size of the LPC134x flash in the host’s folder with the default name
‘firmware.bin’. The ‘firmware.bin’ file can be deleted and a new file can be copied into the
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 19: LPC13xx Flash memory programming firmware
UM10375
© NXP B.V. 2010. All rights reserved.
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