LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 252

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 247. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit
UM10375
User manual
Bit
0
1
2
3
4
31:5
description
Symbol
MR0 Interrupt
MR1 Interrupt
MR2 Interrupt
MR3 Interrupt
CR0 Interrupt
-
14.8.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
14.8.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and
14.8.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and
14.8.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 248. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR -
TMR16B1TC - address 0x4001 0008)
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
TMR16B1PR - address 0x4001 000C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
TMR16B1PC - address 0x4001 0010)
The 16-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Bit
0
1
31:2
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Reserved
Symbol
Counter Enable When one, the Timer Counter and Prescale Counter are
Counter Reset
-
address 0x4001 0004) bit description
All information provided in this document is subject to legal disclaimers.
Description
enabled for counting. When zero, the counters are
disabled.
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Rev. 2 — 7 July 2010
Chapter 14: LPC13xx 16-bit timer/counters (CT16B0/1)
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
0
0
-
Reset value
0
0
NA
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