LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 31

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
3.5.35 System tick counter calibration register
3.5.36 Start logic edge control register 0
Table 39.
Table 40.
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This
register selects a falling or rising edge on the corresponding PIO input to produce a falling
or rising clock edge, respectively, for the start logic (see
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see
register, the top 8 interrupts are contained in the STARTAPRP1 register for total of 40
wake-up interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
Table 41.
Bit
3:2
4
31:5
Bit
25:0
31:26
Bit
0
Symbol
APRPIO0_0
Symbol
BODINTVAL
BODRSTENA
-
Symbol
CAL
-
BOD control register (BODCTRL, address 0x4004 8150) bit description
System tick timer calibration register (SYSTCKCAL, address 0x4004 8158) bit
description
Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
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Value
0
1
Value
00
01
10
11
0
1
-
Value
-
Rev. 2 — 7 July 2010
Description
Edge select for start logic input PIO0_0
Falling edge
Rising edge
Table
Description
BOD interrupt level
The interrupt assertion threshold voltage is 1.69 V; the
interrupt de-assertion threshold voltage is 1.84 V.
The interrupt assertion threshold voltage is 2.29 V; the
interrupt de-assertion threshold voltage is 2.44 V.
The interrupt assertion threshold voltage is 2.59 V; the
interrupt de-assertion threshold voltage is 2.74 V.
The interrupt assertion threshold voltage is 2.87 V; the
interrupt de-assertion threshold voltage is 2.98 V.
BOD reset enable
Disable reset function.
Enable reset function.
Reserved
Description
System tick timer calibration value
Reserved
61). The bottom 32 interrupts are contained this
Chapter 3: LPC13xx System configuration
Section
3.9.2).
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
32 of 333
Reset
value
0x00
0x00
Reset
value
<tbd>
0x00
0x0