LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 205

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
12.10.2 Address Registers, I2ADDR0 to I2ADDR3
12.10.3 Address mask registers, I2MASK0 to I2MASK3
12.10.4 Comparator
12.10.5 Shift register, I2DAT
12.10.6 Arbitration and synchronization logic
These registers may be loaded with the 7-bit slave address (7 most significant bits) to
which the I
LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave
addresses are enabled, the actual address received may be read from the I2DAT register
at the state where the own slave address has been received.
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADDRn register associated with that mask
register. In other words, bits in an I2ADDRn register which are masked are not taken into
account in determining an address match.
If the I2ADDRn bit 0 (GC enable bit) is as set and bits(7:1) are all zeroes, then the part will
respond to a received address = “0000000” regardless of the state of the associated mask
register.
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine what the received address was that actually caused the match.
The comparator compares the received 7-bit slave address with its own slave address (7
most significant bits in I2ADR). It also compares the first received 8-bit byte with the
General Call address (0x00). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
This 8-bit register contains a byte of serial data to be transmitted or a byte which has just
been received. Data in I2DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received
data is located at the MSB of I2DAT. While data is being shifted out, data on the bus is
simultaneously being shifted in; I2DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in I2DAT.
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1
actually appears as a logic 1 on the I
1 and pulls the SDA line low, arbitration is lost, and the I
from master transmitter to slave receiver. The I
pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I
Arbitration is lost when another device on the bus pulls this signal low. Since this can
occur only at the end of a serial byte, the I
Figure 28
shows the arbitration procedure.
2
C block will respond when programmed as a slave transmitter or receiver. The
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
2
C block is returning a “not acknowledge: (logic 1) to the bus.
2
C-bus. If another device on the bus overrules a logic
2
C block generates no further clock pulses.
Chapter 12: LPC13xx I2C-bus controller
2
C block will continue to output clock
2
C block immediately changes
UM10375
© NXP B.V. 2010. All rights reserved.
207 of 333