LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 144

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
UM10375
User manual
9.11.10 Select Endpoint (Command: 0x00 - 0x09 Data: read 1 byte (optional))
Table 175. Get Error Code command description
The Select Endpoint command initializes an internal pointer to the start of the selected
buffer in EP_RAM. Optionally, this command can be followed by a data read, which
returns some additional information on the packet(s) in the endpoint buffer(s). The
command code of the Select Endpoint command is equal to the physical endpoint
number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.
Table 176. Select Endpoint command description
Bit
3:0
4
7:5
Bit Symbol
0
1
FE
ST
Symbol Value
EC
EA
-
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
Description
Error Code.
No Error.
PID Encoding Error.
Unknown PID.
Unexpected Packet - any packet sequence violation from the
specification.
Error in Token CRC.
Error in Data CRC.
Time Out Error.
Babble.
Error in End of Packet.
Sent/Received NAK.
Sent Stall.
Buffer Overrun Error.
Sent Empty Packet (ISO Endpoints only).
Bitstuff Error.
Error in Sync.
Wrong Toggle Bit in Data PID, ignored data.
The Error Active bit will be reset once this register is read.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Full/Empty. This bit indicates the full or empty status of the
endpoint buffer(s). For IN endpoints, the FE bit gives the
ANDed result of the B_1_FULL and B_2_FULL bits. For OUT
endpoints, the FE bit gives ORed result of the B_1_FULL and
B_2_FULL bits. For single buffered endpoints, this bit simply
reflects the status of B_1_FULL.
For an IN endpoint, at least one write endpoint buffer is empty.
For an OUT endpoint, at least one endpoint read buffer is full.
Stalled endpoint indicator.
The selected endpoint is not stalled.
The selected endpoint is stalled.
Rev. 2 — 7 July 2010
Chapter 9: LPC13xx USB device controller
UM10375
© NXP B.V. 2010. All rights reserved.
146 of 333
Reset
value
0
0
Reset
value
0x0
NA

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