LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 237

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
13.7.3 SSP0 Data Register (SSP0DR - 0x4004 0008)
13.7.4 SSP0 Status Register (SSP0SR - 0x4004 000C)
Table 236: SSP0 Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description
Software can write data to be transmitted to this register, and read data that has been
received.
Table 237: SSP0 Data Register (SSP0DR - address 0x4004 0008) bit description
This read-only register reflects the current status of the SSP controller.
Bit
0
1
2
3
31:4
Bit
15:0
31:16 -
Symbol
LBM
SSE
MS
SOD
-
Symbol
DATA
All information provided in this document is subject to legal disclaimers.
Description
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SSP controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bit, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SSP controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bit, the data is right-justified in this
field with higher order bits filled with 0s.
Reserved.
Value
0
1
0
1
0
1
Rev. 2 — 7 July 2010
Description
Loop Back Mode.
During normal operation.
Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
SSP Enable.
The SSP controller is disabled.
The SSP controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SSP registers and interrupt
controller registers, before setting this bit.
Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
The SSP controller acts as a slave on the bus, driving
MISO line and receiving SCLK, MOSI, and SSEL lines.
Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SSP controller
from driving the transmit data line (MISO).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 13: LPC13xx SSP
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x0000
-
0
Reset
value
0
0
0
NA
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