LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 277
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
LPC1313FBD48,151
Manufacturer:
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17.1 How to read this chapter
17.2 Basic configuration
17.3 Features
17.4 Applications
UM10375
User manual
The WDT block is identical for all LPC13xx parts.
The WDT is configured using the following registers:
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15
3. Peripheral clock: Select the WDT clock source
•
•
•
•
•
•
•
•
UM10375
Chapter 17: LPC13xx WatchDog Timer (WDT)
Rev. 2 — 7 July 2010
peripheral clock by writing to the WDTCLKDIV register
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 32 bit timer with internal pre-scaler.
Selectable time period from (T
T
The Watchdog clock (WDCLK) source is selected in the syscon block from the
Internal RC oscillator (IRC), the main clock, or the Watchdog oscillator, see
This gives a wide range of potential timing choices for Watchdog operation under
different power reduction conditions. For increased reliability, it also provides the
ability to run the Watchdog timer from an entirely internal source that is not dependent
on an external crystal and its associated components and wiring.
WDCLK
× 4.
All information provided in this document is subject to legal disclaimers.
Table
13) before using the watchdog oscillator for the WDT.
Rev. 2 — 7 July 2010
WDCLK
× 256 × 4) to (T
(Table
WDCLK
(Table
31) and enable the WDT
(Table
× 2
23).
33).
32
× 4) in multiples of
© NXP B.V. 2010. All rights reserved.
User manual
Table
279 of 333
13.
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