LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 60

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
5.6.5 Interrupt Set-Pending Register 0 register
Table 66.
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or
for reading the pending state of those interrupts. The remaining interrupts can have their
pending state set via the ISPR1 register
interrupts is done through the ICPR0 and ICPR1 registers
Section
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 67.
Bit
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31:25
Bit
0
1
2
3
4
5
6
Name
ISP_PIO0_0
ISP_PIO0_1
ISP_PIO0_2
ISP_PIO0_3
ISP_PIO0_4
ISP_PIO0_5
ISP_PIO0_6
Name
ICE_CT16B0
ICE_CT16B1
ICE_CT32B0
ICE_CT32B1
ICE_SSP
ICE_UART
ICE_USBIRQ
ICE_USBFRQ
ICE_ADC
ICE_WDT
ICE_BOD
-
ICE_PIO_3
ICE_PIO_2
ICE_PIO_1
ICE_PIO_0
-
5.6.8).
Interrupt Clear-Enable Register 1 register (ICER1 - address 0xE000 E184) bit
description
Interrupt Set-Pending Register 0 register (ISPR0 - address 0xE000 E200) bit
description
All information provided in this document is subject to legal disclaimers.
Description
PIO0_0 start logic input interrupt pending set.
PIO0_1 start logic input interrupt pending set.
PIO0_2 start logic input interrupt pending set.
PIO0_3 start logic input interrupt pending set.
PIO0_4 start logic input interrupt pending set.
PIO0_5 start logic input interrupt pending set.
PIO0_6 start logic input interrupt pending set.
…continued
Description
Timer CT16B0 interrupt disable.
Timer CT16B1 interrupt disable.
Timer CT32B0 interrupt disable.
Timer CT32B1 interrupt disable.
SSP interrupt disable.
UART interrupt disable.
USB IRQ interrupt disable.
USB FRQ interrupt disable.
ADC interrupt disable.
WDT interrupt disable.
BOD interrupt disable.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
GPIO port 3 interrupt disable.
GPIO port 2 interrupt disable.
GPIO port 1 interrupt disable.
GPIO port 0 interrupt disable.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
(Section
Chapter 5: LPC13xx Interrupt controller
5.6.6). Clearing the pending state of
(Section 5.6.7
UM10375
© NXP B.V. 2010. All rights reserved.
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