LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 213

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 227. Master Receiver mode
UM10375
User manual
Status
Code
(I2CSTAT)
0x08
0x10
0x38
0x40
0x48
0x50
0x58
Status of the I
and hardware
A START condition
has been transmitted.
A Repeated START
condition has been
transmitted.
Arbitration lost in NOT
ACK bit.
SLA+R has been
transmitted; ACK has
been received.
SLA+R has been
transmitted; NOT ACK
has been received.
Data byte has been
received; ACK has
been returned.
Data byte has been
received; NOT ACK
has been returned.
2
C-bus
Application software response
To/From I2DAT
Load SLA+R
Load SLA+R or
Load SLA+W
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
or
No I2DAT action
Read data byte or 0
Read data byte
Read data byte or 1
Read data byte or 0
Read data byte
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
To I2CON
STA STO SI
X
X
X
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Chapter 12: LPC13xx I2C-bus controller
Next action taken by I
SLA+R will be transmitted; ACK bit will be
received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/TRX mode.
I
enter a slave mode.
A START condition will be transmitted
when the bus becomes free.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be received; NOT ACK bit
will be returned.
Data byte will be received; ACK bit will be
returned.
Repeated START condition will be
transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
2
C-bus will be released; the I
UM10375
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
C block will
2
C block
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