LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 267

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 262: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
Table 263. External match control
UM10375
User manual
Bit
0
1
2
3
5:4
7:6
9:8
11:10
31:12
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
EMC3
-
bit description
15.8.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
00
01
10
11
Description
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of
this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of
this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of
this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of
this output. This bit is driven to the CT32B0_MAT3/CT32B1_MAT3 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match Control 0. Determines the functionality of External Match 0.
shows the encoding of these bits.
External Match Control 1. Determines the functionality of External Match 1.
shows the encoding of these bits.
External Match Control 2. Determines the functionality of External Match 2.
shows the encoding of these bits.
External Match Control 3. Determines the functionality of External Match 3.
shows the encoding of these bits.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 15: LPC13xx 32-bit timer/counters (CT32B0/1)
Table 263
Table 263
Table 263
Table 263
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
00
00
00
00
NA
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