LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 56

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 62.
UM10375
User manual
Name
IPR9
IPR10
IPR11
IPR12
IPR13
IPR14
STIR
RW
RW
Access Address
RW
RW
RW
RW
WO
Register overview: NVIC (base address 0xE000 E000)
5.6.1 Interrupt Set-Enable Register 0 register
0x428
0x42C
offset
0x424
0x430
0x434
0x438
0xF00
The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are enabled via the ISER1
register
registers
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 enables the interrupt.
Read — 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 63.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
ISE_PIO0_0
ISE_PIO0_1
ISE_PIO0_2
ISE_PIO0_3
ISE_PIO0_4
ISE_PIO0_5
ISE_PIO0_6
ISE_PIO0_7
ISE_PIO0_8
ISE_PIO0_9
ISE_PIO0_10
ISE_PIO0_11
ISE_PIO1_0
ISE_PIO1_1
ISE_PIO1_2
(Section
Description
Interrupt Priority Registers 9 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 10 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 11 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 12 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 13 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 14 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Software Trigger Interrupt Register. This register allows software to generate an
interrupt.
(Section 5.6.3
Interrupt Set-Enable Register 0 register (ISER0 - address 0xE000 E100) bit
description
All information provided in this document is subject to legal disclaimers.
5.6.2). Disabling interrupts is done through the ICER0 and ICER1
Description
PIO0_0 start logic input interrupt enable.
PIO0_1 start logic input interrupt enable.
PIO0_2 start logic input interrupt enable.
PIO0_3 start logic input interrupt enable.
PIO0_4 start logic input interrupt enable.
PIO0_5 start logic input interrupt enable.
PIO0_6 start logic input interrupt enable.
PIO0_7 start logic input interrupt enable.
PIO0_8 start logic input interrupt enable.
PIO0_9 start logic input interrupt enable.
PIO0_10 start logic input interrupt enable.
PIO0_11 start logic input interrupt enable.
PIO1_0 start logic input interrupt enable.
PIO1_1 start logic input interrupt enable.
PIO1_2 start logic input interrupt enable.
and
Rev. 2 — 7 July 2010
Section
5.6.4).
…continued
Chapter 5: LPC13xx Interrupt controller
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
0
0
0
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