LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 200

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
12.9 I
UM10375
User manual
2
C operating modes
12.8.10 I
12.9.1 Master Transmitter mode
Although the DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Table 220. I
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADDRn register associated with that mask
register. In other words, bits in an I2ADDRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine what the received address was that actually caused the match.
Table 221. I
In a given application, the I
mode, the I
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
immediately and can detect its own slave address in the same serial transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the I2CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
Bit
7:0
31:8 -
Bit
0
7:1
31:8
2
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])
Symbol
Data
Symbol
-
MASK
-
description
2
2
2
C hardware looks for any one of its four slave addresses and the General Call
C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C) bit description
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C]) bit
All information provided in this document is subject to legal disclaimers.
Description
This register holds contents of the 8 MSBs of the I2DAT shift
register.
Reserved. The value read from a reserved bit is not defined.
Description
Reserved. User software should not write ones to reserved
bits. This bit reads always back as 0.
Mask bits.
Reserved. The value read from reserved bits is undefined.
Rev. 2 — 7 July 2010
2
C block may operate as a master, a slave, or both. In the slave
2
C function. If the AA bit is 0, the I
2
C block switches to the slave mode
Chapter 12: LPC13xx I2C-bus controller
2
C interface will not
UM10375
© NXP B.V. 2010. All rights reserved.
Table
Reset value
0
0x00
0
Reset value
0
0
222. I2EN
202 of 333