LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 23

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
3.5.17 System AHB clock divider register
3.5.18 System AHB clock control register
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 21.
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
Table 22.
The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral
blocks. The system clock (sys_ahb_clk[0], bit 0 in the SYSAHBCLKCTRL register)
provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M3, the
Syscon block, and the PMU. This clock cannot be disabled.
Table 23.
Bit
0
31:1
Bit
7:0
31:8
Bit
0
1
Symbol
ENA
-
Symbol
DIV
-
Symbol
SYS
ROM
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
to
255
-
Value
0
1
-
Value
0
1
0
1
Rev. 2 — 7 July 2010
Description
System AHB clock divider values
System clock disabled.
Divide by 1
...
Divide by 255
Reserved
Description
Enable main clock source update
No change
Update clock source
Reserved
Description
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M3 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
Reserved
Enabled
Enables clock for ROM.
Disabled
Enabled
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x00
Reset
value
1
1
24 of 333
Reset
value
0x01
0x00