LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 147
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
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9.12 USB device controller initialization
UM10375
User manual
9.11.14 Validate Buffer (Command: 0xFA, Data: none)
9.12.1 USB clock configuration
Table 178. Clear Buffer command description
When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See
Remark: For sending an empty packet, the Validate Buffer command should also be
used.
The LPC134x USB device controller initialization includes initialization of the USB clock
and the device controller.
Bit
0
7:1 -
1. Enable the PLL for USB clock if the PLL is used.
2. Set the system oscillator control register SYSOSCCTRL (see
3. Enable the system oscillator by clearing bit 5 in the PDAWAKECFG register (see
4. Select the system clock source by setting 0x01 (use system oscillator) in
5. Update the clock source by setting 1 in SYSPLLUEN register (see
6. Boost system PLL to 192 MHz and then divide by 4 (M=4, P=2) to obtain the 48 MHz
to 0.
Table
SYSPLLCLKSEL register (see
and wait until clock source is updated.
main clock. If the main clock is not 48 MHz then the USB PLL has to be used as USB
clock.
Section 9.13 “Functional description”
Symbol Value Description
PO
51), then wait 200 μs for system oscillator to stabilize.
0
1
-
All information provided in this document is subject to legal disclaimers.
Packet over-written bit. This bit is only applicable to the control
endpoint EP0.
The previously received packet is intact.
The previously received packet was over-written by a later SETUP
packet.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 7 July 2010
Table
16).
for a description of when this command is used.
Chapter 9: LPC13xx USB device controller
Table
UM10375
Table
© NXP B.V. 2010. All rights reserved.
12)
17) register,
149 of 333
Reset
value
0
NA
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